Mixel Inc | Mixed-Signal Excellence
Tradeoffs, Challenges, and Adoption
About the Author:
Ashraf Takla
President & CEO, Mixel, Inc.
First published April 2018. Updated March 2022.
MIPI® C-PHY℠, arrived in October 2014 to a mixture of excitement and apprehension. How would this new C-PHY compare to the MIPI D-PHY℠ and M-PHY®? What would differentiate the C-PHY, and would it be compatible enough with the D-PHY so that both could coexist in a hybrid subsystem?
Now, years later, the answers are clear.
This article will lay out each of those answers, providing a high-level overview of both the D-PHY and C-PHY architecture, highlighting similarities and differences, identifying the pros and cons of each PHY, and providing insight into some of the challenges encountered while implementing the C-PHY. Finally, we will look at Mixel®’s innovative implementation of the C-PHY/D-PHY Combo IP, silicon results from multiple sources, cover uses cases, and examine the adoption of the C-PHY/D-PHY Combo solution in the marketplace.
Let’s begin by taking a closer look at the D-PHY, which has been around since 2009, and thus better understood, and widely deployed. The D-PHY is a simple source synchronous PHY that uses one clock lane and a varying number of data lanes. The block diagram of the four-data lane D-PHY is shown in Figure 1 and the details of each lane are presented in Figure 2. Since the D-PHY has been in the market for almost a decade, there is an abundance of literature available covering its unique features and use-cases (1).
In contrast,the C-PHY isanewer and more complexPHY. Itoperates on three signals, a trio, and the clock is embedded into the data,rendering a separate clock lane unnecessary.The block diagram of the C-PHYis shown in Figure 3.
Table 1 compares between the D-PHY and C-PHY.
Notes: (1) Four data D-PHY lanes vs. three MIPI C-PHY trios
(2) Higher bandwidth due to Encoding
The C-PHY uses encoded data to pack 16/7 ≈ 2.28bits/symbol, while the D-PHY does not useany encoding. Because of that,the C-PHY can achieveahigher data rateascompared to the D-PHY,whilerunningat the sametransitionor symbolrate.
At first glance,theworkingsof theC-PHY,as well asa potential C-PHY/D-PHY combination,may seemmysterious. The C-PHY signaling is multi-level, but its receiver does not need to detect the difference between themulti-level! How can that be? How can the C-PHY and D-PHY, not only coexist, but be efficiently combined into one IPdespitetheirclear differences?The D-PHY uses differential signaling, while the C-PHY uses a trio.Is it possible for them towork together?How can acombo C-PHY/D-PHY be efficiently implemented,usingallthe D-PHY buildingblocks,without any duplication?Where does the ratio 16/7 for the number of data bits per symbols come from? So many questions!
Let usattempt to answer these questionsbyfirsttrying to demystify the C-PHY. Not an easy task! InFigure 4below, we providea quick overviewof the C-PHY. The block diagramin Figure 4(a) showshow a three-lane C-PHY TX and RX areconnected. Figure 4(b) shows the differentsub-blocks of aC-PHYsub-system, namelymapping, Parallel/serialfunction,encoding, and the channel. Figure 4(c) isa more detailed picture of the interaction between the TX and RX, and Figure 4(d), illustrates the C-PHY signaling levels.
A C-PHY lane is composed of a trio, A, B, and C as shown in Figure 4 (c) above. The C-PHY’s receiver is made of 3 differential RX’s, each one looking at the difference between 2 of the 3 signals, (A-B), (B-C), and (C-A).
The C-PHY’s encoder guarantees that (i) there is at least one edge/transition per symbol, (ii) that the differential input at all three RX’s is non-zero, and (iii) that the common mode of all 3 signals is constant. Item (ii) and (iii) above are achieved by restricting the combination of the TX signals during any single Unit Interval (UI) to high, mid, and low, and by keeping the voltage level on each of the three signals different.The combination of the three TX signal levels, high, mid, and low, that comply with restriction (i) above gives 6 different signal level combinations (wire states). The number of wire states, six, is the permutation of the three TX signal levels, 3!Additionally, the C-PHY encoder encodes the Flip, Rotate, Polarity symbol into a state changes based on the encoder rules.
To guarantee that there is at least one edge per symbol, item (i) above, the C-PHY must transition between different wire states as it moves from one symbol to the next and cannot stay at the same wire-state for two consecutive symbols. Because of that restriction, there are five different unique transitions between the six wire states. This means that the encoded data has five different possibilities i.e. each symbol has five possible states, making the C-PHY a base-5 system, or Quinary system. We are then moving between a binary system and a Quinary system. This why the C-PHY mapper is needed.Now that we are using a base-5 system, the maximum theoretical number of bits/symbol is log2(5) = 2.3219. The mapper function was constructed to enable the mapping ratio to be as close as possible without exceeding that theoretical limit. Additionally, the mapper must map between two integer numbers.The Ratio 16/7 ≈ 2.28 was chosen to achieve the above restrictions.
Another way to describe this is that the mapper needs to map 16 binary bits to a certain number of C-PHY symbols, buthow do we determine how many symbol (S) do we mapto?Onthe parallel interfacethere are 2^16 combinationsand the combinations at the output of the mapper are 5^S => 2^16, soS = 7.
To understand the reason why the C-PHY receiver only needs to detect the input signal polarity, and not the amplitude of the multi-amplitude signaling, we only need to remember that there is no data imbedded in signal amplitude. Multi-amplitude signaling is only utilized to increase the number of possible transitions and guarantee that there is least one transition per symbol.
One way to doan apple-to-apple comparisonbetweenperformance ofthe C-PHY andD-PHY, is to comparethem when they aresupporting an aggregate data rate of 4.0Gbpsandoperating atasimilar transition rate.ForD-PHYthis can be accomplished by usingfour-lane D-PHY, using10 wires,each Lanerunning at 1.0Gbps/lane.To obtain the same aggregate data rate at the same or lower transitionratewith C-PHY, we can use two-lanes C-PHY,with6 wires, running at 0.875Gsps,which is less thanthe 1.0Gsps for the D-PHY. In that case,the aggregate data rate for the C-PHY is 2* 0.875 * 16/7 = 4Gbps.This comparison is shown in Figure 6below.
Based on thiscomparison,theC-PHY hasfewer wires (up to 40% less), lowerToggle Rate/Lane (12.5% lower), lower Power Consumption (~20-50% lower), a smaller number of lanes, thus smaller area for sameGbps, and no Emissions from a Clock Lane.
Thus whencomparingthe C-PHY and D-PHY at the same aggregate data rate, the C-PHY has manyadvantages;fewer pins and balls (due to higher performance per pin), flexibility, sinceeach C-PHY lane isindependent,with embedded clock,making it possible toborrow one lane from one link to another,whilecoexistingon the same pins with MIPI D-PHY.The C-PHY also allows lowerpower at higher data rate applications. Furthermore,C-PHY’s embedded clock laneenables assignment of any lane on the Application Processor to any link, andeliminatesclockspur emissions, which is particularly important in multi-band wireless devices.
C-PHY’s embedded control codesalsoenableefficient support of emerging featuressuch asfast Bus Turn Around (BTA) operations, lower latency (LRTE) for time-sensitive links, and AlternateLow Power mode (ALP),whichwould enable longer reach by eliminating single-ended LP mode,resultingin area reduction. Finally, the C-PHY’slower toggle rate often simplifies manufacturing and lowers costsof low cost products, such as low-end cameras.
Nowthat we havegone over the individual attributes of both the C-PHY and D-PHY,we cannumerate some of the advantages oftheC-PHY and D-PHYcombo. This includesbeing able toshareserial interface pins,reusing the LP (Low Power) mode, sharingofcommon blocks, resulting in area reduction,power/Gbpsreduction, a smooth transition between MIPI D-PHY and MIPI C-PHY andtaking advantage of MIPI C-PHYPower/Performance/area (PPA)improvements, while maintaining compatibility with MIPI D-PHY.
Mixel’simplementation of C-PHY/D-PHY Combo IP is unique. All theD-PHY blocks are reused for C-PHYoperation (HS-TX, HS-RX, SER, DESER, LP-TX, LP-RX and LP-CD),minimizing the area overhead for C-PHY support.While allblocks were reused,theEncoder, Decoder, CDR, Mapper and De-Mapper are additional blocks that are needed for C-PHY functionality.Theblock diagram of theMixelimplementation is shown in Figure 7below.
The ComboC-PHY/D-PHYhas been implemented in many different nodes and foundries byMixel. In fact, Mixel’s MIPI IP is silicon proven in 12 different nodes and at 8 different foundries.
Below we show the test setup and siliconevaluation for the C-PHY and D-PHY transmitters.
Below we show the test setup and siliconevaluation for the C-PHY and D-PHY receiver.
Now, let us look at thepower,performance, and area, for different use-cases in current display and camera applications. These are shown in.
There is small area increase when comparing the D-PHY and C-PHY/D-PHY combo at the same data rate. The normalized power of the C-PHY only module, when compared at the same Gbps is comparable. The C-PHY has a clear advantage in enabling higher data rates than the D-PHY at the same transition rate.
However, the power increment combo PHY can be cancelled by enabling multiple design options in C-PHY mode configuration(not shown here).
Display
Camera
Notes:
- Combo PHY areaincrement <10%
- Combo PHY cancover wide range ofResolutions:80Mpbs–10Gbps–17.1Gbps –18Gbps–23.94Gbps
- MIPI C-PHYmode:~10-30%lower power than DPHY mode because oflowfrequency/ smaller bias / lesser # of lanes
- Courtesy of QUALCOMM
The C-PHY/D-PHY combo has gained wide adoption in multiple use-cases,by many differentvendors,and in many different types of products, includingcamera(Sony,OVT,and others),display(interoperability testing completed with most Major DDIC companies). The ecosystem is supported by wide participation covering IP (Mixel), AP/SOC (Snapdragon and others), testers (Keysight, Tektronix, Introspect, The Moving Pixel Company), and common-mode filters(Murata, Panasonic, TDK).
The higher performance of the C-PHY does not come for free; however. There are challenges that come with the C-PHY,includinga unique CDR that requires programming for different data rate rages, multi-level signal transmission, which introduces encoding jitter, and a unique trio-based signalingthat complicates PCB design.
In conclusion, the MIPI C-PHY isamorecomplex,morepowerful and efficient PHY and the C-PHY/D-PHY combo is even more so on all accounts.Mixelhas createdand silicon-proventheDual Mode MIPI D-PHY/ MIPI C-PHY,enabling a smooth transition between the two PHY’s.Mixel’sDual Mode MIPI D-PHY/ MIPI C-PHY sharesallcommon blocks, resulting in area reduction, and reduced power/Gbps. Ithas the benefit of the MIPI C-PHY PPA improvements, while maintaining compatibility with MIPI D-PHY, and using the same serial interface pins. Furthermore, The MIPI C-PHY/MIPI D-PHY combo is silicon-proven in multiple nodes and foundries and has been integrated into several end products by many tier-one SOC, sensor, and display vendors. Since its debut, we have seen acceleratingtraction for MIPI C-PHY/MIPI D-PHY combofor bothcamerasand displaysin a variety of applications including mobile and mobile adjacent applications such as VR/AR/MR, automotive, IoT, and others.
To learn more about Mixel’s silicon-proven IP, please visit mixel.com/ip-cores or Mixel’s contact page.
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